1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit.
2. Description of the Prior Art
The fundamental operation of a conventional PLL circuit is explained.
In FIG. 5, an example of the fundamental PLL circuit is shown. Phase detector (PD) 1 accepts an external input signal frequency fi and a feedback signal frequency f.sub.0 /N which is generated by multiplying the output signal frequency f.sub.0 from voltage controlled oscillator (VCO) 4 by 1/N in frequency divider 5. PD 1 compares the frequencies and phases of fi and f.sub.0 /N and then, outputs pulse signals PU and PD corresponding to the differences between them. Then, the outputs from PD 1 are fed into charge pump 2. Charge pump 2 converts the pulse signals PU and PD into analog quantities and outputs them to low pass filter (LPF) 3. LPF 3 eliminates the high frequency component and noise in the output signal from charge pump 2 and output it as V.sub.0 to VCO 4. VCO 4 outputs the output signal frequency f.sub.0 The output signal frequency f.sub.0 multiplied by 1/N in frequency divider 5 is fed back into PD 1.
As explained above, the PLL circuit repeats these operations and stabilizes the frequency output of the input signal frequency fi multiplied by N, when the input signal fi becomes equal to the feedback signal frequency f.sub.0 /N. However, it is desirable to shorten the time (pull-in time) required to lock the PLL circuit until fi becomes equal to f.sub.0 /N, because the PLL circuit is a kind of frequency negative feedback circuit which acts to detect the differences of the phases between the input signal and the feed-back signal. Therefore, there is disclosed, for example, in the Japanese Patent laid-open No. Hei 8-228148 (1996), a technique wherein the time (lock-in time) required to lock the PLL circuit can be reduced, when the input signal frequency is changed.
In FIG. 6, a block diagram of the PLL circuit disclosed in the JP 8-228148 is shown. Here, only the differences from the conventional circuit shown in FIG. 5 are explained. When the strobe signal STB as well as the set-up frequency data DA is inputted into PLL processing unit 7, the set-up frequency data DA is written in PLL processing unit 7 on the basis of the clock signal CK. Then, PLL processing unit 7 divides the set-up frequency data DA on the basis of the standard frequency of quartz oscillator 6 and outputs the set-up signal fr into PD 1. The strobe signal STB is also fed to analog switch 108 which is connected in parallel with LPF 3. Analog switch 108 is closed only when the strobe signal STB is active. Accordingly, only when the set-up signal fr from PLL processing unit 7 is changed by the change of the set-up frequency data DA, the output SG1 from charge pump 2 is inputted into VCO 4 without passing through LPF 3. Thus, he lock-up time required to transit the frequency from the original frequency to the newly set-up frequency can be shortened. On the other hand, when set-up frequency data DA is not changed, the signal purity (frequency stability) is maintained, because analog switch 108 is not closed and output SG 1 from charge pump 2 passes through LPF 3.
The PLL circuit compares the phase difference between the input signal and the feedback signal, then, eliminates, by using the LPF, the high frequency component and noise of the signal voltage corresponding to the phase difference, and finally outputs from the VCO 4 the frequency on the basis of the output of the LPF. Then, the frequency output is frequency-divided and fed-back until the input signal frequency becomes equal to the feedback signal frequency. Therefore, the conventional PLL circuit has a problem that the pull-in time is required until the input signal frequency becomes identical to the feedback signal frequency. The pull-in in time depends upon the initial frequency, the phase difference between the input signal and the feedback signal, loop gain, and the time constant of the LPF. If the time constant of the LPF is reduced, the noise is not eliminated adequately and signal purity (frequency stability) is degraded, although the pull-in time is reduced. On the other hand, the conventional PLL circuit as shown in FIG. 6 can reduce the lock-up time in case of the change of the set-up frequency without degrading the signal purity (frequency stability), because the feed back signal by-passes the LPF, if the set-up frequency is changed. However, this by-pass technology is not effective for the reduction of the pull-in time.